(1) Field of the Invention
The invention relates to a device for protecting integrated circuits from electrostatic discharge (ESD), and more particularly, to a novel diode device for ESD protection in multiple supply applications.
(2) Description of the Prior Art
The fabrication of disparate functions onto single integrated circuit chips often requires that more than one voltage supply be used. For example, an integrated circuit device may have a low voltage section wherein very small MOS logic transistors are powered from a low voltage supply. This same integrated circuit device may contain analog circuits or input/output (I/O) circuits that are powered by a high voltage supply. In these cases, special design and layout consideration must be used to handle these differing voltage supplies on the chip. In addition, interface circuits, such as level shifting circuits, provide special challenges to insure that the integrated circuit device is not damaged during normal operation or during special transient conditions.
Electrostatic discharge (ESD) is of particular concern for integrated circuits containing more than one voltage supply. ESD events occur primarily due to handling of the integrated circuit by machines or by people. During an ESD event, a large electrostatic potential can develop between pins of the device. When the potential is discharged, energy is dissipated within the device and can result in catastrophic damage to the chip. ESD protection devices are designed on each input and output pin to provide conductive paths between the pin and ground or the pin and the voltage supply during the large voltage transient associate with the ESD event. These protection devices are typically sufficient to protect the I/O pads of the single supply chip. However, when more than one voltage supply pin is used, the ESD protection devices must be modified or additional protection structures must be added.
Referring now to FIG. 1, a partial top view of a prior art integrated circuit device 10 is illustrated. In this device 10, three pads 12, 14, and 16 are shown. In this case, the device 10 uses two voltage supplies, VCC1 and VCC2. In normal operation, the VCC1 voltage is connected to the VCC1 pad 16 and the VCC2 voltage is connected to the VCC2 pad 14. An additional ESD protection device 22 is added to the integrated circuit device 10. This additional ESD protection device 22 is illustrated as a diode 22. The third pad, GND 12, is connected to the ground reference for the system using the integrated circuit device.
Referring now to FIG. 2, a cross-section of an exemplary diode protection device is shown. This device comprises a p-well region 26 in the semiconductor substrate. In practice, the entire semiconductor substrate may be a lightly doped p-type region 26. The p-well region 26 is connected to the GND pad 32. An n-well region 34 is formed in the p-well region 26. An n+region 42 and a p+ region 38 are formed in the n-well region. The n+ region 42 is connected to the VCC1 supply 44, and the p+ region 38 is connected to the VCC2 supply 40. A p-n junction is formed by the p+ region 38 and the n-well region 34. This p-n junction forms the p-n diode 22 that is shown in both FIGS. 1 and 2. This diode structure 22 provides isolation between the VCC2 supply 40 and the VCC1 supply 44 assuming that VCC2 is greater than VCC1 by an amount of less than the diode turn on voltage (Vt) that is typically about 0.7 Volts. When an ESD event occurs, the diode provides a current path between the voltage supply pins that protects the internal circuitry from damage. A distinct disadvantage of the device of FIG. 2 is that VCC2 supply can only be a maximum of about 0.7 Volts greater than the VCC1 supply.
Referring now to FIG. 3, the useful operating range of the diode device of FIG. 2 can be extended by creating a string of diodes. In this prior art device, two n-well regions 66 and 78 are formed. A first diode 80 is formed in the first n-well region 66 by the p-n junction formed by the p+ region 62 and the n-well region 66. The p-terminal 62 of the first diode 80 is connected to the higher voltage source, VCC264. The n-terminal, formed as the n+ regions 58, of the first diode 80 is connected to the p-terminal 74 of the second diode 88. The n-terminal, formed by the n+ regions 70, of the second diode 88 is then connected to the lower voltage source, VCC172. Note that the presence of the n-well regions 66 and 78 in the p-well region 48 actually creates a chain of two p-n-p transistors with two diode drops between VCC2 and VCC1. This means that the diode string configuration allows for the VCC2 voltage to exceed the VCC1 voltage by two diode drops, or about 1.4 Volts.
Referring now to FIG. 4, the prior art diode string concept is shown in the general configuration wherein a large string of p-n-p transistors 112, 116, 120, and 124 are used in the case where a large voltage difference exists between VCC2100 and VCC1104. The diode string approachs used in FIGS. 3 and 4 have the disadvantage of requiring a lot of area to form the separate n-well regions for each stage of the string. In addition, the conductivity of the diodes during an ESD event is not optimal.
Several prior art inventions describe ESD devices and circuits. U.S. Pat. No. 6,002,568 to Ker et al discloses an ESD circuit using silicon controlled rectifier (SCR) devices. U.S. Pat. No. 5,898,205 to Lee teaches an ESD protection circuit where conventional CMOS protection transistors are capacitively-coupled to improve performance. U.S. Pat. No. 6,011,681 to Ker et al discloses a circuit using bi-directional SCR devices to provide current discharge paths between separate power supplies. U.S. Pat. No. 5,530,612 to Maloney teaches ESD protection circuits using biased diode strings and cantilevered diode strings. U.S. Pat. No. 5,747,834 to Chen et al discloses a bipolar SCR with an adjustable holding voltage wherein the device is entirely constructed in an n-well and uses a buried layer.
A principal object of the present invention is to provide an effective and very manufacturable integrated circuit device for protecting the integrated circuit from electrostatic discharge (ESD) events.
A further object of the present invention is to provide an ESD protection device that is effective as a discharge path between voltage supply pins on the same integrated circuit device.
A yet further object of the present invention is to provide an ESD protection device that is suitable for applications wherein a large voltage difference exists between the voltage supply pins.
A still further object of the present invention is to provide an ESD protection device that is suitable for large voltage differences between the voltage supply pins and that can be integrated in a single n-well of small area.
In accordance with the objects of this invention, a new electrostatic discharge protection device is achieved. A p-well region is in a semiconductor substrate. An n+ region in the p-well region is connected to a first voltage supply. An n-well region in the p-well region is spaced from the n+ region such that a depletion region will extend therebetween during normal operation. A p+ region in the n-well region is connected to a second voltage supply of greater value than the first voltage supply during normal operation. Current is conducted through the n+ region to the p+ region during an electrostatic discharge event.